1. Field of the Invention
The invention relates to integrated circuit design and verification, and more particularly to an automatic clock skew indicating circuit.
2. Description of the Related Art
Advances in silicon technology have allowed designers to develop integrated circuits (ICs) with operating clock rates that were once considered unobtainable. In high-speed system design, one of the major problems is clock skew. Clock skew is the result of minor variations in the time at which clocks signals arrive at their destinations, usually IC chip clock pins. If the variations become large, then data may not be reliably clocked in and out of the IC chips. High performance systems require minimum clock skew to keep IC chips functioning properly. In practical systems, one of the critical issues is the length of clock traces on the PCB. In addition to PCB traces, cables, connectors, and chip sockets can contribute to clock skew. Moreover, even a same clock generator has pin-to-pin skew between any two outputs with identical frequency. For example, the allowable skew between clock outputs running at 100 MHz cannot exceed a maximum of 150 ps. As clock rates increase, management of clock skew becomes more susceptible to circuit design, PCB layout, and clock generator characteristics.
IC designers, system engineers, and PCB manufactures are confronted with the challenge of clock skew measurement and verification. Oscilloscopes and logic analyzer are the primary instruments used to probe any high-speed system. When attaching a test instrument to a device under test (DUT), the probe always affects the measurement in some fashion. For a timing measurement, this is directly translated into error in clock skew. It is possible to unintentionally ignore the skew problem due to improper measurement. The underlying clock skew may not be found until after the pilot run and verification procedure. Significant time and money are, however, expended. Accordingly, a way to automatically and effectively identify clock skew within high-speed ICs is required.